High performance VLSI architecture for advanced QPSK modems

DOI: 10.31673/2412-9070.2022.045459

Abstract

The article is devoted to the topical issue of creating a high-performance VLSI architecture for advanced QPSK modems. The QPSK modulation scheme is used in VLSI architecture for many high-speed applications such as satellite communications. VLSI is a technology by which 10,000-1 million transistors can be manufactured on a single chip. Since there was a need for additional functions of electronic devices, the development of NVIS technology improved. The proposed architecture is modeled in XILINX software. This software product is specialized tools for programming programmable logic devices in hardware description languages. The main goal of the research is to create a high-performance QPSK module, thanks to which it supports satellite communication with high bandwidth and energy efficiency. A QPSK modulator is a binary (base 2) signal that produces four different sets of input combinations: 00, 01, 10, and 11. Therefore, with QPSK, binary input combinations are combined from two bits. In the proposed project, 8-PSK and 16-PSK modulation with the basics of QPSK modulation and demodulation system were analyzed and modeled to obtain the required output. VERILOG coding was used for program simulation. Verilog is a hardware description language (HDL) used to model electronic systems. Verilog can run on both Windows 7, 8 and Windows 10 operating systems.
Errors are coded and checked using XILINX software. This project is implemented to create high performance in NVIS using QPSK, 8-PSK, 16-PSK systems used for satellite communication. Implementing this process in any other module is easy, but in NVIS it is a big challenge.

Keywords: QPSK; NVIS; modulation; communication; architecture; demodulation; XILINX; methods.

References
1. Muthukumaran N., Ravi R. Design and analysis of VLSI based FELICS Algorithm for lossless Image Compression // International Journal of Advanced Research in Technology. 2012. Vol. 2, No. 3. Р. 115–119.
2. Cordesses L. Direct digital synthesis: atool for periodic wave generation // IEEE signal process. 2004. Mag, vol. 21, no. 4. Р. 50–54.
3. FPGA implementation of M-PSK modulators for satellite communication / S. Sharma, K. Sunil, V. Pujari [et al.] // Int. conf. Advances in recent technologies in communication and computing. October 2010. P. 16–17
4. Muthukumaran N. Analyzing Throughput of MANET with Reduced Packet Loss // Wireless Personal Communications. 2017. Vol. 97, No. 1. P. 565–578.
5. Venkateswari P., Jebitha Steffy E., Muthukumaran Dr. N. License Plate cognizance by Ocular Character Perception // International Research Journal of Engineering and Technology. 2018. Vol. 5, No. 2. P. 536–542.
6. Rieth D., Heller C., Ascheid g. FPGA implementation of shaped offset QPSK modulator // IEEE Int. conf. Digital signal processing. 2015. P. 790–793.
7. Muthukumaran N., Ravi R. The Performance Analysis of Fast Efficient Lossless Satellite Image Compression and Decompression for Wavelet Based Algorithm // Wireless Personal Communications. 2015. Vol. 81, No. 2. P. 839–859.
8. Muthukumaran N., Ravi R. Hardware Implementation of Architecture Techniques for Fast Efficient loss less Image Compression System // Wireless Personal Communications. 2016. Vol. 90, No. 3. P. 1291–1315.
9. Automatic Enemy Detecting Defense Robot by using Face Detection Technique / B. Renuka, B. Sivaranjani, A. Maha Lakshmi, Dr. N. Muthukumaran // Asian Journal of Applied Science and Technology. 2018. Vol. 2, No. 2. P. 495–501.
10. Finger Print Based Smart Voting System / M. Varsha Peter, V. Priya, H. Petchammal, N. Muthukumaran // Asian Journal of Applied Science and Technology. 2018. Vol. 2, No. 2. P. 357–361.
11. Muthukumaran N., Ravi R. Simulation Based VLSI Implementation of Fast Efficient Lossless ImageCompression System using Simplified Adjusted Binary Code &Golumb Rice Code // World Academy of Science,Engineering and Technology. 2014. Vol. 8, No. 9. P. 1603–1606.